(1) Field of the Invention
The present invention relates to a bipolar lateral transistor and method of fabricating it, more particularly to a method that allows the simultaneous fabrication of FET (Field Effect Transistor) devices.
(2) Description of the Prior Art
Aside from improvements in material quality, improved performance of transistors, both bipolar and field effect, has been achieved by successful reduction of the dimensions of the various subregions that, together, constitute a transistor. Examples of parameters that need to be minimized in order to optimize device performance are emitter-base and collector-base capacitances. These parameters decrease as emitter and collector area, respectively, are reduced in size. Similarly, switching speed increases as the base width (emitter-to-collector distance) is decreased.
Reductions in the dimensions of the various subregions of transistor devices were effected by means of improved photoresist and associated techniques, such as, for example, etching methods. As the limits of what could be achieved by these techniques approached, other ways of bringing about these reductions had to be found.
One such approach to the problem of device size reduction has been the lateral transistor. In conventional, or planar, transistors incorporated as part of integrated circuits, the emitter dimensions (for example) are limited by what can be achieved by masking and etching a planar surface. Thus, if the emitter is to take the shape of a rectangle, its lesser dimension (or line width) is, for planar technology, limited by the state of the masking and etching art--presently about 0.5 microns.
The lateral transistor geometry derives from the fact that the thickness of a layer, be it a diffusion region or a deposited film, can be controlled to much tighter tolerances than can line width, as discussed above. Typically, layer thicknesses can be controlled to better than 0.01 microns. This fact is utilized in lateral transistor design by, in effect, making cross-sections of one or more layers and then using the resulting exposed regions to define the various subareas of the device.
In order to achieve this cross-sectioning effect, processes for making lateral transistors have centered around providing a pedestal, or mesa, that protrudes above the surrounding surface of the integrated circuit, the actual transistor being now in part constructed along the vertical edges of said pedestal. An example of the use of such a structure to create a lateral transistor can be seen in U.S. Pat. No. 4,743,565, May 10 1988, by G. R. Goth and S. D. Malaviya. A similar structure, also employing a mesa, has been described by Cook and Pelella in U.S. Pat. No. 5,187,109, February 1993.
A disadvantage of both these examples of lateral transistors is that a major portion of the device is higher than the plane of the surrounding integrated circuit. This makes it difficult to achieve full planarization of the total surface, leading in turn to difficulties in any subsequent alignment and registration steps that have yet to be performed to complete the manufacture of the integrated circuit, for example the provision of inter-device wiring.